///////////////////////////////////////////////////////////////////////////////
//
// IAR C/C++ Compiler V2.10.4.157 for STM8                13/Jul/2020  10:55:03
// Copyright 2010-2015 IAR Systems AB.
//
//    Source file  =  F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\stm8l15x_pwr.c
//    Command line =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\stm8l15x_pwr.c -e -Ol
//        --no_cse --no_unroll --no_inline --no_code_motion --no_tbaa
//        --no_cross_call --debug --code_model small --data_model medium -o
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\Obj\ --dlib_config
//        E:\IAR\stm8\LIB\dlstm8smf.h -lB
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\inc\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\USER\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\radio\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\ --vregs 16
//    List file    =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\stm8l15x_pwr.s
//
///////////////////////////////////////////////////////////////////////////////

        EXTERN ?b0
        EXTERN ?b1
        EXTERN ?b2

        PUBLIC PWR_DeInit
        PUBLIC PWR_FastWakeUpCmd
        PUBLIC PWR_GetFlagStatus
        PUBLIC PWR_PVDClearFlag
        PUBLIC PWR_PVDClearITPendingBit
        PUBLIC PWR_PVDCmd
        PUBLIC PWR_PVDGetITStatus
        PUBLIC PWR_PVDITConfig
        PUBLIC PWR_PVDLevelConfig
        PUBLIC PWR_UltraLowPowerCmd

// F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\stm8l15x_pwr.c
//    1 /**
//    2   ******************************************************************************
//    3   * @file    stm8l15x_pwr.c
//    4   * @author  MCD Application Team
//    5   * @version V1.6.0
//    6   * @date    28-June-2013
//    7   * @brief   This file provides firmware functions to manage the following 
//    8   *          functionalities of the Power Controller (PWR) peripheral:           
//    9   *           - PVD configuration
//   10   *           - Ultra Low Power mode configuration
//   11   *           - Interrupts and flags management
//   12   *               
//   13   ******************************************************************************
//   14   *
//   15   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
//   16   * You may not use this file except in compliance with the License.
//   17   * You may obtain a copy of the License at:
//   18   *
//   19   *        http://www.st.com/software_license_agreement_liberty_v2
//   20   *
//   21   * Unless required by applicable law or agreed to in writing, software 
//   22   * distributed under the License is distributed on an "AS IS" BASIS, 
//   23   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//   24   * See the License for the specific language governing permissions and
//   25   * limitations under the License.
//   26   *
//   27   ****************************************************************************** 
//   28   */
//   29 
//   30 /* Includes ------------------------------------------------------------------*/
//   31 #include "stm8l15x_pwr.h"
//   32 
//   33 /** @addtogroup STM8L15x_StdPeriph_Driver
//   34   * @{
//   35   */
//   36 
//   37 /** @defgroup PWR 
//   38   * @brief PWR driver modules
//   39   * @{
//   40   */
//   41   
//   42 /* Private typedef -----------------------------------------------------------*/
//   43 /* Private define ------------------------------------------------------------*/
//   44 /* Private macro -------------------------------------------------------------*/
//   45 /* Private variables ---------------------------------------------------------*/
//   46 /* Private function prototypes -----------------------------------------------*/
//   47 /* Private functions ---------------------------------------------------------*/
//   48 
//   49 /** @defgroup PWR_Private_Functions
//   50   * @{
//   51   */
//   52 
//   53 /** @defgroup PWR_Group1 PVD configuration functions
//   54  *  @brief   PVD configuration functions 
//   55  *
//   56 @verbatim   
//   57  ===============================================================================
//   58                            PVD configuration functions
//   59  ===============================================================================  
//   60 
//   61  - The PVD is used to monitor the VDD power supply by comparing it to a threshold
//   62    selected by the PVD Level (PLS[2:0] bits in the PWR_CSR1).
//   63  - The PVD can use an external input analog voltage (PVD_IN) which is compared 
//   64    internally to VREFINT. The PVD_IN (PE6) has to be configured in Analog mode 
//   65    when PWR_PVDLevel_PVDIn is selected (PLS[2:0] = 111).
//   66  - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
//   67    PVD threshold. An interrupt is generated in case enabled for PVD. 
//   68  - The PVD interrup event has the capability to wake up the CPU from Halt/Active Halt modes.
//   69 
//   70 @endverbatim
//   71   * @{
//   72   */
//   73     
//   74 /**
//   75   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
//   76   * @param  None
//   77   * @retval None
//   78   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   79 void PWR_DeInit(void)
//   80 {
//   81   PWR->CSR1 = PWR_CSR1_PVDIF;
PWR_DeInit:
        MOV       L:0x50b2, #0x20
//   82   PWR->CSR2 = PWR_CSR2_RESET_VALUE;
        MOV       L:0x50b3, #0x0
//   83 }
        RET
//   84 
//   85 /**
//   86   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
//   87   * @param  PWR_PVDLevel: specifies the PVD detection level
//   88   *          This parameter can be one of the following values:
//   89   *            @arg PWR_PVDLevel_1V85: PVD detection level set to 1.85V
//   90   *            @arg PWR_PVDLevel_2V05: PVD detection level set to 2.05V
//   91   *            @arg PWR_PVDLevel_2V26: PVD detection level set to 2.26V
//   92   *            @arg PWR_PVDLevel_2V45: PVD detection level set to 2.45V
//   93   *            @arg PWR_PVDLevel_2V65: PVD detection level set to 2.65V
//   94   *            @arg PWR_PVDLevel_2V85: PVD detection level set to 2.85V
//   95   *            @arg PWR_PVDLevel_3V05: PVD detection level set to 3.05V
//   96   *            @arg PWR_PVDLevel_PVDIn: External input analog voltage (Compare internally to VREFINT)
//   97   * @retval None
//   98   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   99 void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel)
//  100 {
PWR_PVDLevelConfig:
        LD        S:?b0, A
//  101   /* Check the parameters */
//  102   assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
//  103 
//  104   /* Clear the PVD level */
//  105   PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PLS);
        LD        A, L:0x50b2
        AND       A, #0xf1
        LD        L:0x50b2, A
//  106 
//  107   /* Configure the PVD level */
//  108   PWR->CSR1 |= PWR_PVDLevel;
        LD        A, S:?b0
        OR        A, L:0x50b2
        LD        L:0x50b2, A
//  109 
//  110 }
        RET
//  111 
//  112 /**
//  113   * @brief  Enables or disables the Power Voltage Detector(PVD).
//  114   * @param  NewState: new state of the PVD.
//  115   *          This parameter can be: ENABLE or DISABLE.
//  116   * @retval None
//  117   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  118 void PWR_PVDCmd(FunctionalState NewState)
//  119 {
//  120   /* Check the parameters */
//  121   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  122 
//  123   if (NewState != DISABLE)
PWR_PVDCmd:
        TNZ       A
        JREQ      L:??PWR_PVDCmd_0
//  124   {
//  125     /* Enable the PWR PVD */
//  126     PWR->CSR1 |= PWR_CSR1_PVDE;
        BSET      L:0x50b2, #0x0
        RET
//  127   }
//  128   else
//  129   {
//  130     /* Disable the PWR PVD */
//  131     PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDE);
??PWR_PVDCmd_0:
        BRES      L:0x50b2, #0x0
//  132   }
//  133 }
        RET
//  134 
//  135 /**
//  136   * @}
//  137   */
//  138 
//  139 /** @defgroup PWR_Group2 Ultra Low Power mode configuration functions
//  140  *  @brief   Ultra Low Power mode configuration functions 
//  141  *
//  142 @verbatim   
//  143  ===============================================================================
//  144                     Ultra Low Power mode configuration functions
//  145  ===============================================================================  
//  146 
//  147  - The internal voltage reference consumption is not negligible, in particular 
//  148    in Halt and Active Halt modes. To reduce power consumption, use the PWR_UltraLowPowerCmd()
//  149    function (ULP bit (Ultra low power) in the PWR_CSR2 register) to disable the 
//  150    internal voltage reference. However, in this case, when exiting from the 
//  151    Halt/Active Halt modes, the functions managed through the internal voltage reference 
//  152    are not reliable during the internal voltage reference startup time (up to 3 ms).
//  153    To reduce the wakeup time, the device can exit from Halt/Active Halt modes without 
//  154    waiting for the internal voltage reference startup time. This is performed 
//  155    by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
//  156    wakeup) in the PWR_CSR2 register) before entering Halt/Active Halt mode.
//  157 
//  158 @endverbatim
//  159   * @{
//  160   */
//  161   
//  162 /**
//  163   * @brief  Enables or disables the Fast WakeUp from Ultra Low Power mode.
//  164   * @param  NewState: new state of the Fast WakeUp  functionality.
//  165   *          This parameter can be: ENABLE or DISABLE.
//  166   * @retval None
//  167   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  168 void PWR_FastWakeUpCmd(FunctionalState NewState)
//  169 {
//  170   /* Check the parameters */
//  171   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  172 
//  173   if (NewState != DISABLE)
PWR_FastWakeUpCmd:
        TNZ       A
        JREQ      L:??PWR_FastWakeUpCmd_0
//  174   {
//  175     /* Enable the PWR FWU */
//  176     PWR->CSR2 |= PWR_CSR2_FWU;
        BSET      L:0x50b3, #0x2
        RET
//  177   }
//  178   else
//  179   {
//  180     /* Disable the PWR FWU */
//  181     PWR->CSR2 &= (uint8_t)(~PWR_CSR2_FWU);
??PWR_FastWakeUpCmd_0:
        BRES      L:0x50b3, #0x2
//  182   }
//  183 }
        RET
//  184 
//  185 /**
//  186   * @brief  Enables or disables the Ultra Low Power mode.
//  187   * @param  NewState: new state of the Ultra Low Power mode.
//  188   *          This parameter can be: ENABLE or DISABLE.
//  189   * @retval None
//  190   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  191 void PWR_UltraLowPowerCmd(FunctionalState NewState)
//  192 {
//  193   /* Check the parameters */
//  194   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  195 
//  196   if (NewState != DISABLE)
PWR_UltraLowPowerCmd:
        TNZ       A
        JREQ      L:??PWR_UltraLowPowerCmd_0
//  197   {
//  198     /* Enable the PWR ULP */
//  199     PWR->CSR2 |= PWR_CSR2_ULP;
        BSET      L:0x50b3, #0x1
        RET
//  200   }
//  201   else
//  202   {
//  203     /* Disable the PWR ULP */
//  204     PWR->CSR2 &= (uint8_t)(~PWR_CSR2_ULP);
??PWR_UltraLowPowerCmd_0:
        BRES      L:0x50b3, #0x1
//  205   }
//  206 }
        RET
//  207 
//  208 /**
//  209   * @}
//  210   */
//  211 
//  212 /** @defgroup PWR_Group3 Interrupts and Flags management functions
//  213  *  @brief   Interrupts and Flags management functions 
//  214  *
//  215 @verbatim   
//  216  ===============================================================================
//  217                  Interrupts and Flags management functions
//  218  ===============================================================================  
//  219 
//  220 @endverbatim
//  221   * @{
//  222   */
//  223 
//  224 /**
//  225   * @brief  Configures the Programmable Voltage Detector (PVD) Interrupt .
//  226   * @param  NewState : Indicates the new state of the PVD interrupt.
//  227   * @retval None
//  228   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  229 void PWR_PVDITConfig(FunctionalState NewState)
//  230 {
//  231   /* Check the parameters */
//  232   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  233 
//  234   if (NewState != DISABLE)
PWR_PVDITConfig:
        TNZ       A
        JREQ      L:??PWR_PVDITConfig_0
//  235   {
//  236     /* Enable the PVD interrupt */
//  237     PWR->CSR1 |= PWR_CSR1_PVDIEN;
        BSET      L:0x50b2, #0x4
        RET
//  238   }
//  239   else
//  240   {
//  241     /* Disable the PVD interrupt */
//  242     PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDIEN);
??PWR_PVDITConfig_0:
        BRES      L:0x50b2, #0x4
//  243   }
//  244 }
        RET
//  245 
//  246 /**
//  247   * @brief  Checks whether the specified PWR flag is set or not.
//  248   * @param  PWR_FLAG: specifies the flag to check.
//  249   *          This parameter can be one of the following values:
//  250   *            @arg PWR_FLAG_PVDOF: PVD Output. This flag is valid only if PVD is enabled 
//  251   *                                 by the PWR_PVDCmd() function.
//  252   *            @arg PWR_FLAG_VREFINTF: Internal Voltage Reference Ready flag. This 
//  253   *                                    flag indicates the state of the internal voltage reference, VREFINT.
//  254   *            @arg PWR_FLAG_PVDIF: PVD Interrupt Flag, it's set by hardware when a PVD
//  255   *       event occurs  
//  256   * @retval The new state of PWR_FLAG (SET or RESET).
//  257   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  258 FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG)
//  259 {
PWR_GetFlagStatus:
        LD        S:?b1, A
//  260   FlagStatus bitstatus = RESET;
        CLR       S:?b0
//  261 
//  262   /* Check the parameters */
//  263   assert_param(IS_PWR_FLAG(PWR_FLAG));
//  264 
//  265   if ((PWR_FLAG & PWR_FLAG_VREFINTF) != 0)
        LD        A, S:?b1
        AND       A, #0x1
        CP        A, #0x0
        JREQ      L:??PWR_GetFlagStatus_0
//  266   {
//  267     if ((PWR->CSR2 & PWR_CR2_VREFINTF) != (uint8_t)RESET )
        BTJF      L:0x50b3, #0x0, L:??PWR_GetFlagStatus_1
//  268     {
//  269       bitstatus = SET;
        MOV       S:?b0, #0x1
        JRA       L:??PWR_GetFlagStatus_2
//  270     }
//  271     else
//  272     {
//  273       bitstatus = RESET;
??PWR_GetFlagStatus_1:
        CLR       S:?b0
        JRA       L:??PWR_GetFlagStatus_2
//  274     }
//  275   }
//  276   else
//  277   {
//  278     if ((PWR->CSR1 & PWR_FLAG) != (uint8_t)RESET )
??PWR_GetFlagStatus_0:
        LD        A, S:?b1
        AND       A, L:0x50b2
        CP        A, #0x0
        JREQ      L:??PWR_GetFlagStatus_3
//  279     {
//  280       bitstatus = SET;
        MOV       S:?b0, #0x1
        JRA       L:??PWR_GetFlagStatus_2
//  281     }
//  282     else
//  283     {
//  284       bitstatus = RESET;
??PWR_GetFlagStatus_3:
        CLR       S:?b0
//  285     }
//  286   }
//  287 
//  288   /* Return the flag status */
//  289   return((FlagStatus)bitstatus);
??PWR_GetFlagStatus_2:
        LD        A, S:?b0
        RET
//  290 }
//  291 
//  292 /**
//  293   * @brief  Clears the PWR PVDIF Flag.
//  294   * @param  None
//  295   * @retval None
//  296   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  297 void PWR_PVDClearFlag(void)
//  298 {
//  299   /* Set the PVDIF to clear it */
//  300   PWR->CSR1 |= PWR_CSR1_PVDIF;
PWR_PVDClearFlag:
        BSET      L:0x50b2, #0x5
//  301 }
        RET
//  302 
//  303 /**
//  304   * @brief  Checks whether the PVD interrupt has occurred or not.
//  305   * @param  None
//  306   * @retval The new state of the PVD Interrupt (SET or RESET).
//  307   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  308 ITStatus PWR_PVDGetITStatus(void)
//  309 {
//  310   ITStatus bitstatus = RESET;
PWR_PVDGetITStatus:
        CLR       S:?b0
//  311 
//  312   uint8_t PVD_itStatus = 0x0, PVD_itEnable = 0x0;
        CLR       S:?b2
        CLR       S:?b1
//  313 
//  314   PVD_itStatus = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIF);
        LD        A, L:0x50b2
        AND       A, #0x20
        LD        S:?b2, A
//  315   PVD_itEnable = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIEN);
        LD        A, L:0x50b2
        AND       A, #0x10
        LD        S:?b1, A
//  316 
//  317   if ((PVD_itStatus != (uint8_t)RESET ) && (PVD_itEnable != (uint8_t)RESET))
        TNZ       S:?b2
        JREQ      L:??PWR_PVDGetITStatus_0
        TNZ       S:?b1
        JREQ      L:??PWR_PVDGetITStatus_0
//  318   {
//  319     bitstatus = (ITStatus)SET;
        MOV       S:?b0, #0x1
        JRA       L:??PWR_PVDGetITStatus_1
//  320   }
//  321   else
//  322   {
//  323     bitstatus = (ITStatus)RESET;
??PWR_PVDGetITStatus_0:
        CLR       S:?b0
//  324   }
//  325   return ((ITStatus)bitstatus);
??PWR_PVDGetITStatus_1:
        LD        A, S:?b0
        RET
//  326 }
//  327 
//  328 /**
//  329   * @brief  Clears the PWR interrupt pending bit.
//  330   * @param  None
//  331   * @retval None
//  332   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  333 void PWR_PVDClearITPendingBit(void)
//  334 {
//  335   /* Set the PVDIF to clear it */
//  336   PWR->CSR1 |= PWR_CSR1_PVDIF;
PWR_PVDClearITPendingBit:
        BSET      L:0x50b2, #0x5
//  337 }
        RET

        SECTION VREGS:DATA:REORDER:NOROOT(0)

        END
//  338 
//  339 /**
//  340   * @}
//  341   */
//  342 
//  343 /**
//  344   * @}
//  345   */
//  346   
//  347 /**
//  348   * @}
//  349   */
//  350 
//  351 /**
//  352   * @}
//  353   */
//  354 
//  355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
// 
// 176 bytes in section .near_func.text
// 
// 176 bytes of CODE memory
//
//Errors: none
//Warnings: none
