///////////////////////////////////////////////////////////////////////////////
//
// IAR C/C++ Compiler V2.10.4.157 for STM8                13/Jul/2020  10:55:04
// Copyright 2010-2015 IAR Systems AB.
//
//    Source file  =  F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\sx1276-LoRa.c
//    Command line =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\sx1276-LoRa.c -e -Ol --no_cse
//        --no_unroll --no_inline --no_code_motion --no_tbaa --no_cross_call
//        --debug --code_model small --data_model medium -o
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\Obj\ --dlib_config
//        E:\IAR\stm8\LIB\dlstm8smf.h -lB
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\inc\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\USER\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\radio\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\ --vregs 16
//    List file    =  F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\sx1276-LoRa.s
//
///////////////////////////////////////////////////////////////////////////////

        EXTERN ?b0
        EXTERN ?b1
        EXTERN ?b10
        EXTERN ?b11
        EXTERN ?b12
        EXTERN ?b13
        EXTERN ?b8
        EXTERN ?epilogue_l2
        EXTERN ?epilogue_l2_w6
        EXTERN ?push_l2
        EXTERN ?push_w6
        EXTERN ?sll16_x_x_4
        EXTERN ?srl8_a_a_5
        EXTERN ?w0
        EXTERN ?w4
        EXTERN ?w5
        EXTERN Flg_1
        EXTERN Flg_2
        EXTERN Flg_2_1
        EXTERN PingMsg
        EXTERN PongMsg
        EXTERN Rssi
        EXTERN strncmp

        PUBLIC BurstWrite
        PUBLIC CR
        PUBLIC RF_IRQ_DS
        PUBLIC RF_IRQ_EN
        PUBLIC SPIBurstRead
        PUBLIC SPICmd8bit
        PUBLIC SPIRead
        PUBLIC SPIRead8bit
        PUBLIC SPIWrite
        PUBLIC SW_Swith_RX
        PUBLIC SW_Swith_TX
        PUBLIC SX1276ConfigTbl
        PUBLIC SX1276Data
        PUBLIC SX1276FSKRateTbl
        PUBLIC SX1276FreqTbl
        PUBLIC SX1276LoRaBwTbl
        PUBLIC SX1276PowerTbl
        PUBLIC SX1276RxTable
        PUBLIC SX1276SpreadFactorTbl
        PUBLIC SX1276TxTable
        PUBLIC SX1276_Config
        PUBLIC SX1276_EntryLoRa
        PUBLIC SX1276_FskClearFIFO
        PUBLIC SX1276_FskConfig
        PUBLIC SX1276_FskEntryRx
        PUBLIC SX1276_FskEntryTx
        PUBLIC SX1276_FskRxPacket
        PUBLIC SX1276_FskTxPacket
        PUBLIC SX1276_LoRaClearIrq
        PUBLIC SX1276_LoRaEntryRx
        PUBLIC SX1276_LoRaEntryTx
        PUBLIC SX1276_LoRaRxPacket
        PUBLIC SX1276_LoRaRxWaitStable
        PUBLIC SX1276_LoRaTxPacket
        PUBLIC SX1276_Sleep
        PUBLIC SX1276_Standby
        PUBLIC Sx1276M_GpioInt
        PUBLIC TxPacketCout
        PUBLIC _A_PB_CR1
        PUBLIC _A_PB_DDR
        PUBLIC _A_PC_CR1
        PUBLIC _A_PC_DDR
        PUBLIC _A_PC_IDR
        PUBLIC _A_PC_ODR
        PUBLIC _A_PD_CR1
        PUBLIC _A_PD_CR2
        PUBLIC _A_PD_DDR
        PUBLIC _A_PD_IDR
        PUBLIC _A_PD_ODR
        PUBLIC _A_PE_CR1
        PUBLIC _A_PE_DDR
        PUBLIC delayms
        PUBLIC gb_BW
        PUBLIC gb_RxData
        PUBLIC gb_SF
        PUBLIC gtmp

// F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\sx1276-LoRa.c
//    1 /*
//    2  * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
//    3  * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
//    4  * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
//    5  * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
//    6  * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
//    7  * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
//    8  * 
//    9  * Copyright (C) SEMTECH S.A.
//   10  */
//   11 /*! 
//   12  * \file       sx1276-LoRa.c
//   13  * \brief      SX1276 RF chip driver mode LoRa
//   14  *
//   15  * \version    2.0.B2 
//   16  * \date       May 6 2013
//   17  * \author     Gregory Cristian
//   18  *
//   19  * Last modified by Miguel Luis on Jun 19 2013
//   20  */
//   21 #include  <iostm8s103f3.h>

        ASEGN `.near.noinit`:DATA:NOROOT,05007H
        SECTION_GROUP _A_PB_DDR
// union <unnamed> volatile _A_PB_DDR
_A_PB_DDR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05008H
        SECTION_GROUP _A_PB_CR1
// union <unnamed> volatile _A_PB_CR1
_A_PB_CR1:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,0500aH
        SECTION_GROUP _A_PC_ODR
// union <unnamed> volatile _A_PC_ODR
_A_PC_ODR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,0500bH
        SECTION_GROUP _A_PC_IDR
// union <unnamed> const volatile _A_PC_IDR
_A_PC_IDR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,0500cH
        SECTION_GROUP _A_PC_DDR
// union <unnamed> volatile _A_PC_DDR
_A_PC_DDR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,0500dH
        SECTION_GROUP _A_PC_CR1
// union <unnamed> volatile _A_PC_CR1
_A_PC_CR1:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,0500fH
        SECTION_GROUP _A_PD_ODR
// union <unnamed> volatile _A_PD_ODR
_A_PD_ODR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05010H
        SECTION_GROUP _A_PD_IDR
// union <unnamed> const volatile _A_PD_IDR
_A_PD_IDR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05011H
        SECTION_GROUP _A_PD_DDR
// union <unnamed> volatile _A_PD_DDR
_A_PD_DDR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05012H
        SECTION_GROUP _A_PD_CR1
// union <unnamed> volatile _A_PD_CR1
_A_PD_CR1:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05013H
        SECTION_GROUP _A_PD_CR2
// union <unnamed> volatile _A_PD_CR2
_A_PD_CR2:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05016H
        SECTION_GROUP _A_PE_DDR
// union <unnamed> volatile _A_PE_DDR
_A_PE_DDR:
        DS8 1

        ASEGN `.near.noinit`:DATA:NOROOT,05017H
        SECTION_GROUP _A_PE_CR1
// union <unnamed> volatile _A_PE_CR1
_A_PE_CR1:
        DS8 1
//   22 #include  <String.h>
//   23 #include "My_type.h"
//   24 #include "sx1276-LoRa.h"
//   25 //#include "main.h"
//   26 
//   27 

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//   28 u8 gb_SF;
gb_SF:
        DS8 1

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//   29 u8  gb_BW;
gb_BW:
        DS8 1

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//   30 u8  CR;	//LR_RegModemConfig1 
CR:
        DS8 1
//   31 
//   32 #define CRC   0x01  //CRC Enable
//   33 
//   34 #define datlen 11
//   35 

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//   36 u8 gtmp;
gtmp:
        DS8 1
//   37 /**********************************************************
//   38 **Parameter table define
//   39 **********************************************************/
//   40 //__root const u16 SX1276FreqTbl[3] = {0x066C, 0x0780, 0x0800}; //434MHz

        SECTION `.near.rodata`:CONST:REORDER:ROOT(0)
//   41 __root const u16 SX1276FreqTbl[3] = {0x0685, 0x073b, 0x0813}; //434MHz @ 26m
SX1276FreqTbl:
        DC16 1669, 1851, 2067
//   42 //__root const u16 SX1276FreqTbl[3] = {0x0634, 0x0700, 0x0800}; //169MHz @ 26m
//   43 

        SECTION `.near.rodata`:CONST:REORDER:ROOT(0)
//   44 __root const u16 SX1276PowerTbl[4] =
SX1276PowerTbl:
        DC16 2559, 2556, 2553, 2550
//   45 { 
//   46   0x09FF,                   //20dbm  
//   47   0x09FC,                   //17dbm
//   48   0x09F9,                   //14dbm
//   49   0x09F6,                   //11dbm 
//   50 };
//   51 

        SECTION `.near.rodata`:CONST:REORDER:ROOT(0)
//   52 __root const u8 SX1276LoRaBwTbl[10] =
SX1276LoRaBwTbl:
        DC8 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
//   53 {// 0        1     2       3      4       5         6      7       8      9
//   54 //7.8KHz,10.4KHz,15.6KHz,20.8KHz,31.2KHz,41.7KHz,62.5KHz,125KHz,250KHz,500KHz
//   55   0,1,2,3,4,5,6,7,8,9
//   56 };
//   57 

        SECTION `.near.rodata`:CONST:REORDER:ROOT(0)
//   58 __root const u8 SX1276SpreadFactorTbl[7] =
SX1276SpreadFactorTbl:
        DC8 6, 7, 8, 9, 10, 11, 12
//   59 {
//   60   6,7,8,9,10,11,12
//   61 };
//   62 
//   63 
//   64 //__root const u8  SX1276Data[datlen] = {"1234567890ABCDEFGHIJK"};

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//   65 u8  SX1276Data[datlen];
SX1276Data:
        DS8 11
//   66 

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//   67 u8  gb_RxData[254];                                         //Receive data buffer
gb_RxData:
        DS8 254
//   68 
//   69 void delayms(unsigned int t)
//   70 {
//   71 	unsigned int i;
//   72 	unsigned char j; 
//   73 	for(i=0;i<t;i++)
//   74 	for(j=0;j<120;j++);
//   75 }
//   76 
//   77 void Sx1276M_GpioInt()
//   78 {
//   79   //*****RF_rst    PD_ODR_ODR2
//   80   PD_DDR_DDR2=1; //OUTPUT
//   81   PD_CR1_C12=1; //SET PD
//   82 
//   83  //***** RF_SCK         PC_ODR_ODR4
//   84   PC_DDR_DDR4=1; //SET PD
//   85   PC_CR1_C14=1; //SET PD
//   86   
//   87   
//   88   //*****RF_MISO       PC_IDR_IDR5 //INPUT
//   89   PC_DDR_DDR5=0; //INPUT
//   90   PC_CR1_C15=1; //PULL-UP-INPUT
//   91 
//   92  //*****RF_MOSI       PC_ODR_ODR6
//   93   PC_DDR_DDR6=1;//OUTPUT
//   94   PC_CR1_C16=1; //SET PD
//   95  
//   96   //*****RF_NSEL_PIN   PC_ODR_ODR7
//   97   PC_DDR_DDR7=1; //OUTPUT
//   98   PC_CR1_C17=1; //SET PD
//   99   
//  100 
//  101   //*****  RF_IRQ       PD_IDR_IDR3
//  102   PD_DDR_DDR3=0; //INPUT
//  103   PD_CR1_C13=1; //PULL-UP-INPUT
//  104   PD_CR2_C23=0; //
//  105 
//  106   //***** LED_TX      PB_ODR_ODR0
//  107   PB_DDR_DDR0=1; //OUTPUT
//  108   PB_CR1_C10=1; //SET PD
//  109   
//  110   //*****   #define LED_RX    PE_ODR_ODR5 //OUTPUT
//  111   PE_DDR_DDR5=1; //OUTPUT
//  112   PE_CR1_C15=1; //SET PD
//  113 
//  114   //*****     #define SW_CTRL1  		PB_ODR_ODR6
//  115   PB_DDR_DDR6=1; //OUTPUT
//  116   PB_CR1_C16=1; //SET PD
//  117 
//  118   //*****   #define SW_CTRL2  		PC_ODR_ODR2
//  119   PC_DDR_DDR2=1; //OUTPUT
//  120   PC_CR1_C12=1; //SET PD
//  121 
//  122   RF_NSEL_PIN=1;
//  123 }
//  124 
//  125 
//  126 void RF_IRQ_DS()
//  127 {
//  128 PD_CR2_C23=0; //关中断
//  129 }
//  130 void RF_IRQ_EN()
//  131 {
//  132 PD_CR2_C23=1; //关中断
//  133 }
//  134 
//  135 
//  136 void SW_Swith_RX()
//  137 {
//  138 //SW_CTRL1=0;
//  139 //SW_CTRL2=1;
//  140 }
//  141 
//  142 void SW_Swith_TX()
//  143 {
//  144 //SW_CTRL1=1;
//  145 //SW_CTRL2=0;
//  146 }
//  147 /**********************************************************
//  148 **Name:     SPICmd8bit
//  149 **Function: SPI Write one byte
//  150 **Input:    WrPara
//  151 **Output:   none
//  152 **note:     use for burst mode
//  153 **********************************************************/
//  154 void SPICmd8bit(u8 WrPara)
//  155 {
//  156   u8 bitcnt;  
//  157   nCS=0;
//  158   SCK=0;
//  159   
//  160   for(bitcnt=8; bitcnt!=0; bitcnt--)
//  161   {
//  162     SCK=0;
//  163     if(WrPara&0x80)
//  164       MOSI=1;
//  165     else
//  166       MOSI=0;
//  167 	asm("nop");	
//  168 	asm("nop");	
//  169     SCK=1;
//  170 	asm("nop");	
//  171     WrPara <<= 1;
//  172   }
//  173   SCK=0;
//  174   MOSI=1;
//  175 }
//  176 
//  177 /**********************************************************
//  178 **Name:     SPIRead8bit
//  179 **Function: SPI Read one byte
//  180 **Input:    None
//  181 **Output:   result byte
//  182 **Note:     use for burst mode
//  183 **********************************************************/
//  184 u8 SPIRead8bit(void)
//  185 {
//  186  u8 RdPara = 0;
//  187  u8 bitcnt;
//  188  
//  189   nCS=0;
//  190   MOSI=1;                                                 //Read one byte data from FIFO, MOSI hold to High
//  191   for(bitcnt=8; bitcnt!=0; bitcnt--)
//  192   {
//  193     SCK=0;
//  194 	asm("nop");	
//  195 	asm("nop");	
//  196     RdPara <<= 1;
//  197     SCK=1;
//  198     if(MISO)
//  199       RdPara |= 0x01;
//  200     else
//  201       RdPara |= 0x00;
//  202   }
//  203   SCK=0;
//  204   return(RdPara);
//  205 }
//  206 
//  207 /**********************************************************
//  208 **Name:     SPIRead
//  209 **Function: SPI Read CMD
//  210 **Input:    adr -> address for read
//  211 **Output:   None
//  212 **********************************************************/
//  213 u8 SPIRead(u8 adr)
//  214 {
//  215   u8 tmp; 
//  216   SPICmd8bit(adr);                                         //Send address first
//  217   tmp = SPIRead8bit();  
//  218   nCS=1;
//  219   return(tmp);
//  220 }
//  221 
//  222 
//  223 /**********************************************************
//  224 **Name:     SPIWrite
//  225 **Function: SPI Write CMD
//  226 **Input:    WrPara -> address & data
//  227 **Output:   None
//  228 **********************************************************/
//  229 void SPIWrite(word WrPara)                
//  230 {                                                       
//  231   u8 bitcnt;    
//  232   
//  233   SCK=0;
//  234   nCS=0;
//  235   
//  236   WrPara |= 0x8000;                                        //MSB must be "1" for write 
//  237   
//  238   for(bitcnt=16; bitcnt!=0; bitcnt--)
//  239   {
//  240     SCK=0;
//  241 	asm("nop");	
//  242 	asm("nop");	
//  243     if(WrPara&0x8000)
//  244       MOSI=1;
//  245     else
//  246       MOSI=0;
//  247     SCK=1;
//  248     WrPara <<= 1;
//  249   }
//  250   SCK=0;
//  251   MOSI=1;
//  252   nCS=1;
//  253 }
//  254 
//  255 /**********************************************************
//  256 **Name:     SPIBurstRead
//  257 **Function: SPI burst read mode
//  258 **Input:    adr-----address for read
//  259 **          ptr-----data buffer point for read
//  260 **          length--how many bytes for read
//  261 **Output:   None
//  262 **********************************************************/
//  263 void SPIBurstRead(u8 adr, u8 *ptr, u8 length)
//  264 {
//  265   u8 i;
//  266   if(length<=1)                                            //length must more than one
//  267     return;
//  268   else
//  269   {
//  270     SCK=0; 
//  271     nCS=0;
//  272     SPICmd8bit(adr); 
//  273     for(i=0;i<length;i++)
//  274     ptr[i] = SPIRead8bit();
//  275     nCS=1;  
//  276   }
//  277 }
//  278 
//  279 /**********************************************************
//  280 **Name:     SPIBurstWrite
//  281 **Function: SPI burst write mode
//  282 **Input:    adr-----address for write
//  283 **          ptr-----data buffer point for write
//  284 **          length--how many bytes for write
//  285 **Output:   none
//  286 **********************************************************/
//  287 void BurstWrite(u8 adr, u8 *ptr, u8 length)
//  288 { 
//  289   u8 i;
//  290 
//  291   if(length<=1)                                            //length must more than one
//  292     return;
//  293   else  
//  294   {   
//  295     SCK=0;
//  296     nCS=0;        
//  297     SPICmd8bit(adr|0x80);
//  298     for(i=0;i<length;i++)
//  299     SPICmd8bit(ptr[i]);
//  300     nCS=1;  
//  301   }
//  302 }
//  303 
//  304 
//  305 /**********************************************************
//  306 **Name:     SX1276_Standby
//  307 **Function: Entry standby mode
//  308 **Input:    None
//  309 **Output:   None
//  310 **********************************************************/
//  311 void SX1276_Standby(void)
//  312 {
//  313   SPIWrite(LR_RegOpMode+0x01+0x08);                              //Standby
//  314 }
//  315 
//  316 /**********************************************************
//  317 **Name:     SX1276_Sleep
//  318 **Function: Entry sleep mode
//  319 **Input:    None
//  320 **Output:   None
//  321 **********************************************************/
//  322 void SX1276_Sleep(void)
//  323 {
//  324   SPIWrite(LR_RegOpMode+0x00+0x08);                              //Sleep
//  325 }
//  326 
//  327 /*********************************************************/
//  328 //LoRa mode
//  329 /*********************************************************/
//  330 /**********************************************************
//  331 **Name:     SX1276_EntryLoRa
//  332 **Function: Set RFM69 entry LoRa(LongRange) mode
//  333 **Input:    None
//  334 **Output:   None
//  335 **********************************************************/
//  336 void SX1276_EntryLoRa(void)
//  337 {
//  338   SPIWrite(LR_RegOpMode+0x80+0x08);//设置成rola模式和低频工作模式
//  339 }
//  340 
//  341 /**********************************************************
//  342 **Name:     SX1276_LoRaClearIrq
//  343 **Function: Clear all irq
//  344 **Input:    None
//  345 **Output:   None
//  346 **********************************************************/
//  347 void SX1276_LoRaClearIrq(void)
//  348 {
//  349   SPIWrite(LR_RegIrqFlags+0xFF);
//  350 }
//  351 
//  352 /**********************************************************
//  353 **Name:     SX1276_Config
//  354 **Function: SX1276 base config
//  355 **Input:    mode
//  356 **Output:   None
//  357 **********************************************************/
//  358 void SX1276_Config(u8 mode)
//  359 {
//  360   u8 i; 
//  361     
//  362   RF_RST=0;
//  363   for(i=150;i!=0;i--)                                      //Delay
//  364     asm("NOP"); 
//  365   
//  366   RF_RST=1;
//  367   
//  368   for(i=100;i!=0;i--)                                      //Delay
//  369     asm("NOP");  
//  370     
//  371   SX1276_Sleep();                                           //Change modem mode Must in Sleep mode 
//  372   for(i=100;i!=0;i--)                                      //Delay
//  373     asm("NOP");  
//  374 
//  375    SPIWrite(REG_LR_TCXO+0x09);                              //USE TCXO晶振相关设置 
//  376 
//  377     SX1276_EntryLoRa();  
//  378     //SPIWrite(0x5904);   //?? Change digital regulator form 1.6V to 1.47V: see errata note
//  379     
//  380     for(i=0;i<3;i++)                                       //setting frequency parameter
//  381     {
//  382       SPIWrite(SX1276FreqTbl[i]);  //设置载波频率
//  383     }
//  384 
//  385     //setting base parameter 
//  386     SPIWrite(SX1276PowerTbl[0]);             //Setting output power parameter  
//  387     
//  388     SPIWrite(LR_RegOcp+0x0B);                              //RegOcp,Close Ocp
//  389     SPIWrite(LR_RegLna+0x23);                              //RegLNA,High & LNA Enable
//  390 
//  391 	
//  392     
//  393     if(SX1276SpreadFactorTbl[gb_SF]==6)           //SFactor=6
//  394     {
//  395       u8 tmp;
//  396       SPIWrite(LR_RegModemConfig1+(SX1276LoRaBwTbl[gb_BW]<<4)+(CR<<1)+0x01);//Implicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04)
//  397       SPIWrite(LR_RegModemConfig2+(SX1276SpreadFactorTbl[gb_SF]<<4)+(CRC<<2)+0x03);
//  398       
//  399       tmp = SPIRead(0x31);
//  400       tmp &= 0xF8;
//  401       tmp |= 0x05;
//  402       SPIWrite(0x3100+tmp);
//  403       SPIWrite(0x3700+0x0C);
//  404     } 
//  405     else
//  406     {
//  407       SPIWrite(LR_RegModemConfig1+(SX1276LoRaBwTbl[gb_BW]<<4)+(CR<<1)+0x00);//Explicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04)
//  408       SPIWrite(LR_RegModemConfig2+(SX1276SpreadFactorTbl[gb_SF]<<4)+(CRC<<2)+0x03);  //SFactor &  LNA gain set by the internal AGC loop 
//  409       SPIWrite(LR_RegModemConfig3+0x08);//LowDataRateOptimize en
//  410     }
//  411     SPIWrite(LR_RegSymbTimeoutLsb+0xFF);                   //RegSymbTimeoutLsb Timeout = 0x3FF(Max) 
//  412     
//  413     SPIWrite(LR_RegPreambleMsb + 0);                       //RegPreambleMsb 
//  414     SPIWrite(LR_RegPreambleLsb + 16);                      //RegPreambleLsb 8+4=12byte Preamble  16+4=20
//  415 /****************************************/    
//  416     u8 temp;   
//  417     temp=SPIRead((u8)(LR_RegPaConfig>>8));
//  418     temp=(temp&0x7F)|0x80;
//  419     SPIWrite(LR_RegPaConfig+temp); //fly
//  420 /****************************************/   
//  421    // SPIWrite(REG_LR_DIOMAPPING2+0x01);                     //RegDioMapping2 DIO5=00, DIO4=01
//  422     SX1276_Standby();                                         //Entry standby mode
//  423 }
//  424 
//  425 /**********************************************************
//  426 **Name:     SX1276_LoRaEntryRx
//  427 **Function: Entry Rx mode
//  428 **Input:    None
//  429 **Output:   None
//  430 **********************************************************/
//  431 void SX1276_LoRaEntryRx(void)
//  432 {
//  433   u8 addr; 
//  434         
//  435   SX1276_Config(0);                                         //setting base parameter
//  436   
//  437   SPIWrite(0x4D00+0x84);                                   //Normal and Rx
//  438   SPIWrite(LR_RegHopPeriod+0xFF);                          //RegHopPeriod NO FHSS
//  439   SPIWrite(REG_LR_DIOMAPPING1+0x01);                       //DIO0=00, DIO1=00, DIO2=00, DIO3=01  DIO0=00--RXDONE
//  440       
//  441   SPIWrite(LR_RegIrqFlagsMask+0x3F);                       //Open RxDone interrupt & Timeout
//  442   SX1276_LoRaClearIrq();   
//  443   
//  444   SPIWrite(LR_RegPayloadLength+datlen);                       //RegPayloadLength  21byte(this register must difine when the data long of one byte in SF is 6)
//  445     
//  446   addr = SPIRead((u8)(LR_RegFifoRxBaseAddr>>8));           //Read RxBaseAddr
//  447   SPIWrite(LR_RegFifoAddrPtr+addr);                        //RxBaseAddr -> FiFoAddrPtr　 
//  448   SPIWrite(LR_RegOpMode+0x0D);                        //Continuous Rx Mode
//  449 
//  450   delayms(10);
//  451 }
//  452 
//  453 /**********************************************************
//  454 **Name:     SX1276_LoRaRxWaitStable
//  455 **Function: Determine whether the state of stable Rx 查询RX 状态
//  456 **Input:    none
//  457 **Output:   none
//  458 **********************************************************/
//  459 u8 SX1276_LoRaRxWaitStable(void)
//  460 { 
//  461 	uint8 tmp;
//  462 	tmp=SPIRead((u8)(LR_RegModemStat>>8));
//  463 	return tmp;
//  464 }
//  465 
//  466 /**********************************************************
//  467 **Name:     SX1276_LoRaRxPacket
//  468 **Function: Receive data in LoRa mode
//  469 **Input:    None
//  470 **Output:   None
//  471 **********************************************************/
//  472 void SX1276_LoRaRxPacket(void)
//  473 {
//  474     u8 addr;
//  475     u8 packet_size;    
//  476     addr = SPIRead((u8)(LR_RegFifoRxCurrentaddr>>8));//last packet addr 数据包的最后地址(数据的尾地址)
//  477     SPIWrite(LR_RegFifoAddrPtr+addr);//RxBaseAddr -> FiFoAddrPtr   
//  478 
//  479     if(SX1276SpreadFactorTbl[gb_SF]==6)//When SpreadFactor is six，will used Implicit Header mode(Excluding internal packet length)
//  480             packet_size=21;
//  481     else
//  482             packet_size = SPIRead((u8)(LR_RegRxNbBytes>>8));//Number for received bytes    
//  483 
//  484     gtmp= packet_size;
//  485     SPIBurstRead(0x00, gb_RxData, packet_size);
//  486     if( strncmp( ( const char* )gb_RxData, ( const char* )PongMsg, 4 ) == 0 )
//  487       Flg_1=1;
//  488     else if( strncmp( ( const char* )gb_RxData, ( const char* )PingMsg, 4 ) == 0 )
//  489       Flg_2=1;
//  490     Rssi = SPIRead((u8)(LR_RegPktRssiValue>>8));
//  491     if(Rssi>137) Rssi=Rssi-137;
//  492     else Rssi=137-Rssi;
//  493     SX1276_LoRaClearIrq();
//  494 }
//  495 
//  496 
//  497 /**********************************************************
//  498 **Name:     SX1276_LoRaEntryTx
//  499 **Function: Entry Tx mode
//  500 **Input:    None
//  501 **Output:   None
//  502 **********************************************************/
//  503 void SX1276_LoRaEntryTx(void)
//  504 {
//  505     u8 addr;
//  506 
//  507     SX1276_Config(0);                                         //setting base parameter
//  508 
//  509     SPIWrite(0x4D00+0x87);                                   //Tx for 20dBm
//  510     SPIWrite(LR_RegHopPeriod);                               //RegHopPeriod NO FHSS
//  511     
//  512     SPIWrite(REG_LR_DIOMAPPING1+0x41);                       //DIO0=01, DIO1=00, DIO2=00, DIO3=01
//  513     SPIWrite(REG_LR_DIOMAPPING2+0x01); //fly                 //RegDioMapping2 DIO5=00, DIO4=01
//  514     
//  515     SX1276_LoRaClearIrq();
//  516     SPIWrite(LR_RegIrqFlagsMask+0xF7);                       //Open TxDone interrupt
//  517     SPIWrite(LR_RegPayloadLength+ datlen);                       //RegPayloadLength  21byte
//  518     SPIWrite(LR_RegFifoTxBaseAddr);//fly
//  519     addr = SPIRead((u8)(LR_RegFifoTxBaseAddr>>8));           //RegFiFoTxBaseAddr
//  520     SPIWrite(LR_RegFifoAddrPtr+addr);                        //RegFifoAddrPtr
//  521 }

        SECTION `.near.data`:DATA:REORDER:NOROOT(0)
//  522 uint16 TxPacketCout=1;
TxPacketCout:
        DC16 1
//  523 /**********************************************************
//  524 **Name:     SX1276_LoRaTxPacket
//  525 **Function: Send data in LoRa mode
//  526 **Input:    None
//  527 **Output:   1- Send over
//  528 **********************************************************/
//  529 void SX1276_LoRaTxPacket(void)
//  530 { 
//  531     u8 tmp;
//  532     delayms(10);        
//  533     if(Flg_2_1==1)
//  534     {
//  535         SX1276Data[0]='P';
//  536         SX1276Data[1]='O';
//  537         SX1276Data[2]='N';
//  538         SX1276Data[3]='G';
//  539         Flg_2_1=0;
//  540     }
//  541     else
//  542     {        
//  543         SX1276Data[0]='P';
//  544         SX1276Data[1]='I';
//  545         SX1276Data[2]='N';
//  546         SX1276Data[3]='G';    
//  547     }
//  548     
//  549     SX1276Data[4]=(TxPacketCout>>8);
//  550     SX1276Data[5]=(u8)(TxPacketCout);
//  551     TxPacketCout++;  
//  552     
//  553     for(tmp=6;tmp<datlen;tmp++)
//  554             SX1276Data[tmp]=tmp;
//  555     
//  556     BurstWrite(0x00, (u8 *)SX1276Data, datlen);
//  557     SPIWrite(LR_RegOpMode+0x03+0x08);                    //Tx Mode       
//  558 }
//  559 
//  560 
//  561 
//  562 ///////////////////////////////////////////////// FSK mode //////////////////////////////////////////////////

        SECTION `.near.rodata`:CONST:REORDER:NOROOT(0)
//  563 const u16 SX1276ConfigTbl[16] = 
SX1276ConfigTbl:
        DC16 1026, 1341, 2827, 3107, 4626, 8096, 9472, 9734, 10130, 10410
        DC16 10541, 10964, 12288, 12608, 12821, 13717
//  564 { 
//  565   0x0402,                   //RegFdevMsb 	35KHz 
//  566   0x053D,                   //RegFdevLsb
//  567   0x0B0B,                   //RegOcp 	Close Ocp
//  568   //0x0C20,                 //RegLNA 	High & LNA Disable
//  569   0x0C23,                   //RegLNA	High & LNA Enable
//  570   0x1212,                   //RegRxBw		83KHz
//  571   0x1FA0,                   //RegPreambleDet	Enable 2Byte 
//  572   //0x1F20,                 //RegPreambleDet	Disable 
//  573   0x2500,                   //RegPreambleMsb  
//  574   0x2606,                   //RegPreambleLsb	6Byte Preamble
//  575   0x2792,                   //RegSyncConfig	Sync 2+1=3bytes
//  576   0x2800+0xAA,              //SyncWord = aa2dd4
//  577   0x2900+0x2D,              //
//  578   0x2A00+0xD4,              //
//  579   0x3000,                   //RegPacketConfig1  Disable CRC，NRZ
//  580   0x3140,                   //RegPacketConfig2  Packet Mode
//  581   0x3215,                   //RegPayloadLength  21bytes Fixed
//  582   0x3595,                   //RegFiFoThresh		21bytes                        
//  583 };
//  584 

        SECTION `.near.rodata`:CONST:REORDER:NOROOT(0)
//  585 const u16 SX1276FSKRateTbl[4][2] = 
SX1276FSKRateTbl:
        DC16 616, 811, 564, 789, 538, 779, 525, 773
//  586 {
//  587   {0x0268, 0x032B},         //BR=1.2Kbps
//  588   {0x0234, 0x0315},         //BR=2.4Kbps
//  589   {0x021A, 0x030B},         //BR=4.8Kbps
//  590   {0x020D, 0x0305},         //BR=9.6Kbps
//  591 };
//  592 

        SECTION `.near.rodata`:CONST:REORDER:NOROOT(0)
//  593 const u16 SX1276RxTable[4] = 
SX1276RxTable:
        DC16 2319, 16396, 16640, 19844
//  594 {       
//  595   0x090F,                   //RFIO Pin
//  596   0x400C,                   //DIO0 Mapping for IRQ / DIO2 for RxData
//  597   0x4100,                   //
//  598   0x4D84,                   //Normal and Rx   
//  599 };
//  600                               

        SECTION `.near.rodata`:CONST:REORDER:NOROOT(0)
//  601 const u16 SX1276TxTable[3] = 
SX1276TxTable:
        DC16 16384, 16640, 19847

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_FskTxPacket:
        MOV       S:?b0, #0x15
        LDW       X, #SX1276Data
        CLR       A
        CALL      L:BurstWrite
        LDW       X, #0x10b
        CALL      L:SPIWrite
        nop
??SX1276_FskTxPacket_0:
        LD        A, L:0x5010
        SRL       A
        SRL       A
        SRL       A
        AND       A, #0x1
        CP        A, #0x0
        JREQ      L:??SX1276_FskTxPacket_0
        JP        L:SX1276_Standby
        REQUIRE _A_PD_IDR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_FskEntryTx:
        PUSH      S:?b8
        CALL      L:SX1276_FskConfig
        CLR       S:?b8
        JRA       L:??SX1276_FskEntryTx_0
??SX1276_FskEntryTx_1:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276FSKRateTbl,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_FskEntryTx_0:
        LD        A, S:?b8
        CP        A, #0x2
        JRC       L:??SX1276_FskEntryTx_1
        CLR       S:?b8
        JRA       L:??SX1276_FskEntryTx_2
??SX1276_FskEntryTx_3:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276TxTable,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_FskEntryTx_2:
        LD        A, S:?b8
        CP        A, #0x3
        JRC       L:??SX1276_FskEntryTx_3
        LDW       X, #0x10b
        CALL      L:SPIWrite
        POP       S:?b8
        RET

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_FskRxPacket:
        LD        A, L:0x5010
        SRL       A
        SRL       A
        SRL       A
        AND       A, #0x1
        CP        A, #0x0
        JREQ      L:??SX1276_FskRxPacket_0
        CLR       S:?b0
        JRA       L:??SX1276_FskRxPacket_1
??SX1276_FskRxPacket_2:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b0
        EXG       A, XL
        CLR       A
        LD        (L:gb_RxData,X), A
        LD        A, S:?b0
        ADD       A, #0x1
        LD        S:?b0, A
??SX1276_FskRxPacket_1:
        LD        A, S:?b0
        CP        A, #0x20
        JRC       L:??SX1276_FskRxPacket_2
        MOV       S:?b0, #0x15
        LDW       X, #gb_RxData
        CLR       A
        CALL      L:SPIBurstRead
        CALL      L:SX1276_FskClearFIFO
        CLR       S:?b0
        JRA       L:??SX1276_FskRxPacket_3
??SX1276_FskRxPacket_4:
        LD        A, S:?b0
        ADD       A, #0x1
        LD        S:?b0, A
??SX1276_FskRxPacket_3:
        LD        A, S:?b0
        CP        A, #0x11
        JRNC      L:??SX1276_FskRxPacket_5
        CLRW      X
        EXG       A, XL
        LD        A, S:?b0
        EXG       A, XL
        LD        A, (L:SX1276Data,X)
        CLRW      X
        EXG       A, XL
        LD        A, S:?b0
        EXG       A, XL
        CP        A, (L:gb_RxData,X)
        JREQ      L:??SX1276_FskRxPacket_4
??SX1276_FskRxPacket_5:
        LD        A, S:?b0
        CP        A, #0x11
        JRC       L:??SX1276_FskRxPacket_6
        LD        A, #0x1
        RET
??SX1276_FskRxPacket_6:
        CLR       A
        RET
??SX1276_FskRxPacket_0:
        CLR       A
        RET
        REQUIRE _A_PD_IDR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_FskEntryRx:
        PUSH      S:?b8
        CALL      L:SX1276_FskConfig
        CLR       S:?b8
        JRA       L:??SX1276_FskEntryRx_0
??SX1276_FskEntryRx_1:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276FSKRateTbl,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_FskEntryRx_0:
        LD        A, S:?b8
        CP        A, #0x2
        JRC       L:??SX1276_FskEntryRx_1
        CLR       S:?b8
        JRA       L:??SX1276_FskEntryRx_2
??SX1276_FskEntryRx_3:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276RxTable,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_FskEntryRx_2:
        LD        A, S:?b8
        CP        A, #0x4
        JRC       L:??SX1276_FskEntryRx_3
        LDW       X, #0x10d
        CALL      L:SPIWrite
        POP       S:?b8
        RET

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_FskClearFIFO:
        LDW       X, #0x101
        CALL      L:SPIWrite
        LDW       X, #0x10d
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_FskConfig:
        PUSH      S:?b8
        BRES      L:0x500f, #0x2
        MOV       S:?b8, #0x64
        JRA       L:??SX1276_FskConfig_0
??SX1276_FskConfig_1:
        NOP
        LD        A, S:?b8
        ADD       A, #0xff
        LD        S:?b8, A
??SX1276_FskConfig_0:
        TNZ       S:?b8
        JRNE      L:??SX1276_FskConfig_1
        BSET      L:0x500f, #0x2
        MOV       S:?b8, #0xfa
        JRA       L:??SX1276_FskConfig_2
??SX1276_FskConfig_3:
        NOP
        LD        A, S:?b8
        ADD       A, #0xff
        LD        S:?b8, A
??SX1276_FskConfig_2:
        TNZ       S:?b8
        JRNE      L:??SX1276_FskConfig_3
        CALL      L:SX1276_Sleep
        MOV       S:?b8, #0xfa
        JRA       L:??SX1276_FskConfig_4
??SX1276_FskConfig_5:
        NOP
        LD        A, S:?b8
        ADD       A, #0xff
        LD        S:?b8, A
??SX1276_FskConfig_4:
        TNZ       S:?b8
        JRNE      L:??SX1276_FskConfig_5
        CLR       S:?b8
        JRA       L:??SX1276_FskConfig_6
??SX1276_FskConfig_7:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276FreqTbl,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_FskConfig_6:
        LD        A, S:?b8
        CP        A, #0x3
        JRC       L:??SX1276_FskConfig_7
        LDW       X, L:SX1276PowerTbl
        CALL      L:SPIWrite
        CLR       S:?b8
        JRA       L:??SX1276_FskConfig_8
??SX1276_FskConfig_9:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276ConfigTbl,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_FskConfig_8:
        LD        A, S:?b8
        CP        A, #0x10
        JRC       L:??SX1276_FskConfig_9
        CALL      L:SX1276_Standby
        POP       S:?b8
        RET
        REQUIRE _A_PD_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_LoRaTxPacket:
        LDW       X, #0xa
        CALL      L:delayms
        LD        A, L:Flg_2_1
        CP        A, #0x1
        JRNE      L:??SX1276_LoRaTxPacket_0
        MOV       L:SX1276Data, #0x50
        MOV       L:SX1276Data + 1, #0x4f
        MOV       L:SX1276Data + 2, #0x4e
        MOV       L:SX1276Data + 3, #0x47
        MOV       L:Flg_2_1, #0x0
        JRA       L:??SX1276_LoRaTxPacket_1
??SX1276_LoRaTxPacket_0:
        MOV       L:SX1276Data, #0x50
        MOV       L:SX1276Data + 1, #0x49
        MOV       L:SX1276Data + 2, #0x4e
        MOV       L:SX1276Data + 3, #0x47
??SX1276_LoRaTxPacket_1:
        LDW       X, L:TxPacketCout
        CLR       A
        RRWA      X, A
        LD        A, XL
        LD        L:SX1276Data + 4, A
        LDW       X, L:TxPacketCout
        LD        A, XL
        LD        L:SX1276Data + 5, A
        LDW       X, L:TxPacketCout
        INCW      X
        LDW       L:TxPacketCout, X
        LD        A, #0x6
        JRA       L:??SX1276_LoRaTxPacket_2
??SX1276_LoRaTxPacket_3:
        CLRW      X
        LD        XL, A
        LD        (L:SX1276Data,X), A
        ADD       A, #0x1
??SX1276_LoRaTxPacket_2:
        CP        A, #0xb
        JRC       L:??SX1276_LoRaTxPacket_3
        MOV       S:?b0, #0xb
        LDW       X, #SX1276Data
        CLR       A
        CALL      L:BurstWrite
        LDW       X, #0x10b
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_LoRaEntryTx:
        CLR       A
        CALL      L:SX1276_Config
        LDW       X, #0x4d87
        CALL      L:SPIWrite
        LDW       X, #0x2400
        CALL      L:SPIWrite
        LDW       X, #0x4041
        CALL      L:SPIWrite
        LDW       X, #0x4101
        CALL      L:SPIWrite
        CALL      L:SX1276_LoRaClearIrq
        LDW       X, #0x11f7
        CALL      L:SPIWrite
        LDW       X, #0x220b
        CALL      L:SPIWrite
        LDW       X, #0xe00
        CALL      L:SPIWrite
        LD        A, #0xe
        CALL      L:SPIRead
        CLRW      X
        LD        XL, A
        ADDW      X, #0xd00
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_LoRaRxPacket:
        LD        A, #0x10
        CALL      L:SPIRead
        CLRW      X
        LD        XL, A
        ADDW      X, #0xd00
        CALL      L:SPIWrite
        LD        A, L:gb_SF
        CLRW      X
        LD        XL, A
        LD        A, #0x6
        CP        A, (L:SX1276SpreadFactorTbl,X)
        JRNE      L:??SX1276_LoRaRxPacket_0
        LD        A, #0x15
        JRA       L:??SX1276_LoRaRxPacket_1
??SX1276_LoRaRxPacket_0:
        LD        A, #0x13
        CALL      L:SPIRead
??SX1276_LoRaRxPacket_1:
        LD        L:gtmp, A
        LD        S:?b0, A
        LDW       X, #gb_RxData
        CLR       A
        CALL      L:SPIBurstRead
        LDW       X, #0x4
        LDW       S:?w0, X
        LDW       Y, #PongMsg
        LDW       X, #gb_RxData
        CALL      L:strncmp
        TNZW      X
        JRNE      L:??SX1276_LoRaRxPacket_2
        MOV       L:Flg_1, #0x1
        JRA       L:??SX1276_LoRaRxPacket_3
??SX1276_LoRaRxPacket_2:
        LDW       X, #0x4
        LDW       S:?w0, X
        LDW       Y, #PingMsg
        LDW       X, #gb_RxData
        CALL      L:strncmp
        TNZW      X
        JRNE      L:??SX1276_LoRaRxPacket_3
        MOV       L:Flg_2, #0x1
??SX1276_LoRaRxPacket_3:
        LD        A, #0x1a
        CALL      L:SPIRead
        CLRW      X
        LD        XL, A
        LDW       L:Rssi, X
        LDW       X, L:Rssi
        CPW       X, #0x8a
        JRSLT     L:??SX1276_LoRaRxPacket_4
        LDW       X, L:Rssi
        ADDW      X, #0xffffffffffffff77
        LDW       L:Rssi, X
        JP        L:SX1276_LoRaClearIrq
??SX1276_LoRaRxPacket_4:
        LDW       X, #0x89
        SUBW      X, L:Rssi
        LDW       L:Rssi, X
        JP        L:SX1276_LoRaClearIrq

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_LoRaRxWaitStable:
        LD        A, #0x18
        JP        L:SPIRead

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_LoRaEntryRx:
        CLR       A
        CALL      L:SX1276_Config
        LDW       X, #0x4d84
        CALL      L:SPIWrite
        LDW       X, #0x24ff
        CALL      L:SPIWrite
        LDW       X, #0x4001
        CALL      L:SPIWrite
        LDW       X, #0x113f
        CALL      L:SPIWrite
        CALL      L:SX1276_LoRaClearIrq
        LDW       X, #0x220b
        CALL      L:SPIWrite
        LD        A, #0xf
        CALL      L:SPIRead
        CLRW      X
        LD        XL, A
        ADDW      X, #0xd00
        CALL      L:SPIWrite
        LDW       X, #0x10d
        CALL      L:SPIWrite
        LDW       X, #0xa
        JP        L:delayms

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_Config:
        PUSH      S:?b8
        BRES      L:0x500f, #0x2
        MOV       S:?b8, #0x96
        JRA       L:??SX1276_Config_0
??SX1276_Config_1:
        NOP
        LD        A, S:?b8
        ADD       A, #0xff
        LD        S:?b8, A
??SX1276_Config_0:
        TNZ       S:?b8
        JRNE      L:??SX1276_Config_1
        BSET      L:0x500f, #0x2
        MOV       S:?b8, #0x64
        JRA       L:??SX1276_Config_2
??SX1276_Config_3:
        NOP
        LD        A, S:?b8
        ADD       A, #0xff
        LD        S:?b8, A
??SX1276_Config_2:
        TNZ       S:?b8
        JRNE      L:??SX1276_Config_3
        CALL      L:SX1276_Sleep
        MOV       S:?b8, #0x64
        JRA       L:??SX1276_Config_4
??SX1276_Config_5:
        NOP
        LD        A, S:?b8
        ADD       A, #0xff
        LD        S:?b8, A
??SX1276_Config_4:
        TNZ       S:?b8
        JRNE      L:??SX1276_Config_5
        LDW       X, #0x4b09
        CALL      L:SPIWrite
        CALL      L:SX1276_EntryLoRa
        CLR       S:?b8
        JRA       L:??SX1276_Config_6
??SX1276_Config_7:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b8
        EXG       A, XL
        SLLW      X
        LDW       X, (L:SX1276FreqTbl,X)
        CALL      L:SPIWrite
        LD        A, S:?b8
        ADD       A, #0x1
        LD        S:?b8, A
??SX1276_Config_6:
        LD        A, S:?b8
        CP        A, #0x3
        JRC       L:??SX1276_Config_7
        LDW       X, L:SX1276PowerTbl
        CALL      L:SPIWrite
        LDW       X, #0xb0b
        CALL      L:SPIWrite
        LDW       X, #0xc23
        CALL      L:SPIWrite
        LD        A, L:gb_SF
        CLRW      X
        LD        XL, A
        LD        A, #0x6
        CP        A, (L:SX1276SpreadFactorTbl,X)
        JRNE      L:??SX1276_Config_8
        LD        A, L:gb_BW
        CLRW      X
        LD        XL, A
        LD        A, (L:SX1276LoRaBwTbl,X)
        CLRW      X
        LD        XL, A
        CALL      L:?sll16_x_x_4
        LDW       Y, X
        LD        A, L:CR
        CLRW      X
        LD        XL, A
        SLLW      X
        LDW       S:?w0, X
        LDW       X, Y
        ADDW      X, S:?w0
        ADDW      X, #0x1d01
        CALL      L:SPIWrite
        LD        A, L:gb_SF
        CLRW      X
        LD        XL, A
        LD        A, (L:SX1276SpreadFactorTbl,X)
        CLRW      X
        LD        XL, A
        CALL      L:?sll16_x_x_4
        ADDW      X, #0x1e07
        CALL      L:SPIWrite
        LD        A, #0x31
        CALL      L:SPIRead
        AND       A, #0xf8
        OR        A, #0x5
        CLRW      X
        LD        XL, A
        ADDW      X, #0x3100
        CALL      L:SPIWrite
        LDW       X, #0x370c
        CALL      L:SPIWrite
        JRA       L:??SX1276_Config_9
??SX1276_Config_8:
        LD        A, L:gb_BW
        CLRW      X
        LD        XL, A
        LD        A, (L:SX1276LoRaBwTbl,X)
        CLRW      X
        LD        XL, A
        CALL      L:?sll16_x_x_4
        LDW       Y, X
        LD        A, L:CR
        CLRW      X
        LD        XL, A
        SLLW      X
        LDW       S:?w0, X
        LDW       X, Y
        ADDW      X, S:?w0
        ADDW      X, #0x1d00
        CALL      L:SPIWrite
        LD        A, L:gb_SF
        CLRW      X
        LD        XL, A
        LD        A, (L:SX1276SpreadFactorTbl,X)
        CLRW      X
        LD        XL, A
        CALL      L:?sll16_x_x_4
        ADDW      X, #0x1e07
        CALL      L:SPIWrite
        LDW       X, #0x2608
        CALL      L:SPIWrite
??SX1276_Config_9:
        LDW       X, #0x1fff
        CALL      L:SPIWrite
        LDW       X, #0x2000
        CALL      L:SPIWrite
        LDW       X, #0x2110
        CALL      L:SPIWrite
        LD        A, #0x9
        CALL      L:SPIRead
        OR        A, #0x80
        CLRW      X
        LD        XL, A
        ADDW      X, #0x900
        CALL      L:SPIWrite
        CALL      L:SX1276_Standby
        POP       S:?b8
        RET
        REQUIRE _A_PD_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_LoRaClearIrq:
        LDW       X, #0x12ff
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_EntryLoRa:
        LDW       X, #0x188
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_Sleep:
        LDW       X, #0x108
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SX1276_Standby:
        LDW       X, #0x109
        JP        L:SPIWrite

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
BurstWrite:
        CALL      L:?push_l2
        LD        S:?b1, A
        LDW       S:?w4, X
        MOV       S:?b11, S:?b0
        LD        A, S:?b11
        CP        A, #0x2
        JRC       L:??BurstWrite_0
        BRES      L:0x500a, #0x4
        BRES      L:0x500a, #0x7
        LD        A, S:?b1
        OR        A, #0x80
        CALL      L:SPICmd8bit
        CLR       S:?b10
        JRA       L:??BurstWrite_1
??BurstWrite_2:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b10
        EXG       A, XL
        ADDW      X, S:?w4
        LD        A, (X)
        CALL      L:SPICmd8bit
        LD        A, S:?b10
        ADD       A, #0x1
        LD        S:?b10, A
??BurstWrite_1:
        LD        A, S:?b10
        CP        A, S:?b11
        JRC       L:??BurstWrite_2
        BSET      L:0x500a, #0x7
??BurstWrite_0:
        JP        L:?epilogue_l2
        REQUIRE _A_PC_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SPIBurstRead:
        CALL      L:?push_l2
        CALL      L:?push_w6
        LD        S:?b1, A
        LDW       S:?w4, X
        MOV       S:?b13, S:?b0
        LD        A, S:?b13
        CP        A, #0x2
        JRC       L:??SPIBurstRead_0
        BRES      L:0x500a, #0x4
        BRES      L:0x500a, #0x7
        LD        A, S:?b1
        CALL      L:SPICmd8bit
        CLR       S:?b12
        JRA       L:??SPIBurstRead_1
??SPIBurstRead_2:
        CLRW      X
        EXG       A, XL
        LD        A, S:?b12
        EXG       A, XL
        ADDW      X, S:?w4
        LDW       S:?w5, X
        CALL      L:SPIRead8bit
        LD        [S:?w5.w], A
        LD        A, S:?b12
        ADD       A, #0x1
        LD        S:?b12, A
??SPIBurstRead_1:
        LD        A, S:?b12
        CP        A, S:?b13
        JRC       L:??SPIBurstRead_2
        BSET      L:0x500a, #0x7
??SPIBurstRead_0:
        JP        L:?epilogue_l2_w6
        REQUIRE _A_PC_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SPIWrite:
        BRES      L:0x500a, #0x4
        BRES      L:0x500a, #0x7
        RLWA      X, A
        OR        A, #0x80
        RLWA      X, A
        OR        A, #0x0
        RLWA      X, A
        MOV       S:?b0, #0x10
        JRA       L:??SPIWrite_0
??SPIWrite_1:
        BRES      L:0x500a, #0x6
??SPIWrite_2:
        BSET      L:0x500a, #0x4
        SLLW      X
        LD        A, S:?b0
        ADD       A, #0xff
        LD        S:?b0, A
??SPIWrite_0:
        TNZ       S:?b0
        JREQ      L:??SPIWrite_3
        BRES      L:0x500a, #0x4
        nop
        nop
        LDW       Y, X
        EXGW      X, Y
        RLWA      X, A
        AND       A, #0x80
        RLWA      X, A
        AND       A, #0x0
        RLWA      X, A
        EXGW      X, Y
        TNZW      Y
        JREQ      L:??SPIWrite_1
        BSET      L:0x500a, #0x6
        JRA       L:??SPIWrite_2
??SPIWrite_3:
        BRES      L:0x500a, #0x4
        BSET      L:0x500a, #0x6
        BSET      L:0x500a, #0x7
        RET
        REQUIRE _A_PC_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SPIRead:
        CALL      L:SPICmd8bit
        CALL      L:SPIRead8bit
        BSET      L:0x500a, #0x7
        RET
        REQUIRE _A_PC_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SPIRead8bit:
        CLR       S:?b1
        BRES      L:0x500a, #0x7
        BSET      L:0x500a, #0x6
        MOV       S:?b0, #0x8
        JRA       L:??SPIRead8bit_0
??SPIRead8bit_1:
        LD        A, S:?b0
        ADD       A, #0xff
        LD        S:?b0, A
??SPIRead8bit_0:
        TNZ       S:?b0
        JREQ      L:??SPIRead8bit_2
        BRES      L:0x500a, #0x4
        nop
        nop
        LD        A, S:?b1
        SLL       A
        LD        S:?b1, A
        BSET      L:0x500a, #0x4
        LD        A, L:0x500b
        CALL      L:?srl8_a_a_5
        AND       A, #0x1
        CP        A, #0x0
        JREQ      L:??SPIRead8bit_1
        LD        A, S:?b1
        OR        A, #0x1
        LD        S:?b1, A
        JRA       L:??SPIRead8bit_1
??SPIRead8bit_2:
        BRES      L:0x500a, #0x4
        LD        A, S:?b1
        RET
        REQUIRE _A_PC_ODR
        REQUIRE _A_PC_IDR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SPICmd8bit:
        LD        S:?b1, A
        BRES      L:0x500a, #0x7
        BRES      L:0x500a, #0x4
        MOV       S:?b0, #0x8
        JRA       L:??SPICmd8bit_0
??SPICmd8bit_1:
        BRES      L:0x500a, #0x6
??SPICmd8bit_2:
        nop
        nop
        BSET      L:0x500a, #0x4
        nop
        LD        A, S:?b1
        SLL       A
        LD        S:?b1, A
        LD        A, S:?b0
        ADD       A, #0xff
        LD        S:?b0, A
??SPICmd8bit_0:
        TNZ       S:?b0
        JREQ      L:??SPICmd8bit_3
        BRES      L:0x500a, #0x4
        LD        A, S:?b1
        AND       A, #0x80
        CP        A, #0x0
        JREQ      L:??SPICmd8bit_1
        BSET      L:0x500a, #0x6
        JRA       L:??SPICmd8bit_2
??SPICmd8bit_3:
        BRES      L:0x500a, #0x4
        BSET      L:0x500a, #0x6
        RET
        REQUIRE _A_PC_ODR

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SW_Swith_TX:
        RET

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
SW_Swith_RX:
        RET

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
RF_IRQ_EN:
        BSET      L:0x5013, #0x3
        RET
        REQUIRE _A_PD_CR2

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
RF_IRQ_DS:
        BRES      L:0x5013, #0x3
        RET
        REQUIRE _A_PD_CR2

        SECTION `.near_func.text`:CODE:NOROOT(0)
        CODE
Sx1276M_GpioInt:
        BSET      L:0x5011, #0x2
        BSET      L:0x5012, #0x2
        BSET      L:0x500c, #0x4
        BSET      L:0x500d, #0x4
        BRES      L:0x500c, #0x5
        BSET      L:0x500d, #0x5
        BSET      L:0x500c, #0x6
        BSET      L:0x500d, #0x6
        BSET      L:0x500c, #0x7
        BSET      L:0x500d, #0x7
        BRES      L:0x5011, #0x3
        BSET      L:0x5012, #0x3
        BRES      L:0x5013, #0x3
        BSET      L:0x5007, #0x0
        BSET      L:0x5008, #0x0
        BSET      L:0x5016, #0x5
        BSET      L:0x5017, #0x5
        BSET      L:0x5007, #0x6
        BSET      L:0x5008, #0x6
        BSET      L:0x500c, #0x2
        BSET      L:0x500d, #0x2
        BSET      L:0x500a, #0x7
        RET
        REQUIRE _A_PD_DDR
        REQUIRE _A_PD_CR1
        REQUIRE _A_PC_DDR
        REQUIRE _A_PC_CR1
        REQUIRE _A_PD_CR2
        REQUIRE _A_PB_DDR
        REQUIRE _A_PB_CR1
        REQUIRE _A_PE_DDR
        REQUIRE _A_PE_CR1
        REQUIRE _A_PC_ODR

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
delayms:
        CLRW      Y
        JRA       L:??delayms_0
??delayms_1:
        ADD       A, #0x1
??delayms_2:
        CP        A, #0x78
        JRC       L:??delayms_1
        INCW      Y
??delayms_0:
        LDW       S:?w0, X
        CPW       Y, S:?w0
        JRNC      L:??delayms_3
        CLR       A
        JRA       L:??delayms_2
??delayms_3:
        RET

        SECTION VREGS:DATA:REORDER:NOROOT(0)

        END
//  602 {
//  603   0x4000,                   //DIO0 Mapping for IRQ / DIO2 for RxData
//  604   0x4100,                   //          
//  605   0x4D87,                   //20dBm Tx
//  606 };
//  607 /**********************************************************
//  608 **Name:     SX1276_Config
//  609 **Function: SX1276 base config
//  610 **Input:    mode
//  611 **Output:   None
//  612 **********************************************************/
//  613 void SX1276_FskConfig()
//  614 {
//  615   u8 i; 
//  616 
//  617  RF_RST=0;
//  618   for(i=100;i!=0;i--)                                      //Delay
//  619     asm("NOP"); 
//  620   
//  621   RF_RST=1;
//  622   
//  623   for(i=250;i!=0;i--)                                      //Delay
//  624     asm("NOP");  
//  625     
//  626   SX1276_Sleep();                                           //Change modem mode Must in Sleep mode 
//  627   for(i=250;i!=0;i--)                                      //Delay
//  628     asm("NOP");  
//  629   
//  630     for(i=0;i<3;i++)                                       //setting frequency parameter
//  631     {
//  632       SPIWrite(SX1276FreqTbl[i]);  
//  633     }
//  634 	
//  635     SPIWrite(SX1276PowerTbl[0]);             //Setting output power parameter
//  636     
//  637     for(i=0;i<16;i++)                                      //setting base parameter
//  638       SPIWrite(SX1276ConfigTbl[i]);
//  639 
//  640   SX1276_Standby();                                         //Entry standby mode
//  641 }
//  642 
//  643 /**********************************************************
//  644 **Name:     SX1276_FskClearFIFO
//  645 **Function: Change to RxMode from StandbyMode, can clear FIFO buffer
//  646 **Input:    None
//  647 **Output:   None
//  648 **********************************************************/
//  649 void SX1276_FskClearFIFO(void)
//  650 {
//  651   SPIWrite(0x0101);                                        //Standby
//  652   SPIWrite(0x0105+0x08);                                   //entry RxMode
//  653 }
//  654 
//  655 /**********************************************************
//  656 **Name:     SX1276_FskEntryRx
//  657 **Function: Set RFM69 entry FSK Rx_mode
//  658 **Input:    None
//  659 **Output:   "0" for Error Status
//  660 **********************************************************/
//  661 void SX1276_FskEntryRx(void)
//  662 {
//  663   u8 i;
//  664   
//  665   SX1276_FskConfig();  
//  666   for(i=0;i<2;i++)
//  667     SPIWrite(SX1276FSKRateTbl[0][i]);         //setting rf rate parameter  1.2kbps
//  668   for(i=0;i<4;i++)                                         //Define to Rx mode 
//  669     SPIWrite(SX1276RxTable[i]);    
//  670   SPIWrite(0x0105+0x08);                                   //entry RxMode
//  671   
//  672 }
//  673 
//  674 
//  675 /**********************************************************
//  676 **Name:     SX1276_FskRxPacket
//  677 **Function: Check for receive one packet
//  678 **Input:    none
//  679 **Output:   "!0"-----Receive one packet
//  680 **          "0"------Nothing for receive
//  681 **********************************************************/
//  682 u8 SX1276_FskRxPacket(void)
//  683 {
//  684   u8 i; 
//  685     
//  686   if(RF_IRQ_DIO0)
//  687   { 
//  688     for(i=0;i<32;i++) 
//  689       gb_RxData[i] = 0x00;  
//  690     
//  691     SPIBurstRead(0x00, gb_RxData, 21);  
//  692     SX1276_FskClearFIFO();
//  693     for(i=0;i<17;i++)
//  694     {
//  695       if(gb_RxData[i]!=SX1276Data[i])
//  696         break;  
//  697     }
//  698     if(i>=17) 
//  699       return(1);                                           //Rx success
//  700     else
//  701       return(0);
//  702   }
//  703   else
//  704     return(0);  
//  705 }
//  706 
//  707 
//  708 
//  709 /**********************************************************
//  710 **Name:     SX1276_FskEntryTx
//  711 **Function: Set SX1276 entry FSK Tx_mode
//  712 **Input:    None
//  713 **Output:   "0" for Error Status
//  714 **********************************************************/
//  715 void SX1276_FskEntryTx(void)
//  716 {
//  717   u8 i;
//  718   
//  719   SX1276_FskConfig();
//  720   for(i=0;i<2;i++)
//  721     SPIWrite(SX1276FSKRateTbl[0][i]);         //setting rf rate parameter  
//  722   for(i=0;i<3;i++)                                         //Define to Tx mode 
//  723     SPIWrite(SX1276TxTable[i]);
//  724   SPIWrite(0x0103+0x08);
//  725       
//  726 }
//  727 
//  728 /**********************************************************
//  729 **Name:     SX1276_FskTxPacket
//  730 **Function: Check SX1276 send over & send next packet
//  731 **Input:    none
//  732 **Output:   TxFlag=1, Send success
//  733 **********************************************************/
//  734 void SX1276_FskTxPacket(void)
//  735 {
//  736 		
//  737 		BurstWrite(0x00, (u8 *)SX1276Data, 21);     
//  738 		SPIWrite(0x0103+0x08);                               //Entry Tx mode
//  739 
//  740 		asm("nop");	
//  741 
//  742 		while(!RF_IRQ_DIO0) ;                    //Packet send over 发送完成了IRQ 变为H,平时L
//  743 
//  744 		SX1276_Standby();                                     //Entry Standby mode      
//  745   
//  746 }
//  747 
//  748 
//  749 
//  750 
//  751 
//  752 
//  753 
// 
//   269 bytes in section .near.bss
//     2 bytes in section .near.data
//    13 bytes in section .near.noinit    (abs)
//    93 bytes in section .near.rodata
// 1 615 bytes in section .near_func.text
// 
// 1 615 bytes of CODE  memory
//    93 bytes of CONST memory
//   271 bytes of DATA  memory (+ 13 bytes shared)
//
//Errors: none
//Warnings: none
