///////////////////////////////////////////////////////////////////////////////
//
// IAR C/C++ Compiler V2.10.4.157 for STM8                13/Jul/2020  10:55:03
// Copyright 2010-2015 IAR Systems AB.
//
//    Source file  =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\stm8l15x_iwdg.c
//    Command line =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\stm8l15x_iwdg.c -e -Ol
//        --no_cse --no_unroll --no_inline --no_code_motion --no_tbaa
//        --no_cross_call --debug --code_model small --data_model medium -o
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\Obj\ --dlib_config
//        E:\IAR\stm8\LIB\dlstm8smf.h -lB
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\inc\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\USER\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\radio\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\ --vregs 16
//    List file    =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\stm8l15x_iwdg.s
//
///////////////////////////////////////////////////////////////////////////////

        PUBLIC IWDG_Enable
        PUBLIC IWDG_ReloadCounter
        PUBLIC IWDG_SetPrescaler
        PUBLIC IWDG_SetReload
        PUBLIC IWDG_WriteAccessCmd

// F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\stm8l15x_iwdg.c
//    1 /**
//    2   ********************************************************************************
//    3   * @file    stm8l15x_iwdg.c
//    4   * @author  MCD Application Team
//    5   * @version V1.6.0
//    6   * @date    28-June-2013
//    7   * @brief   This file provides firmware functions to manage the following 
//    8   *          functionalities of the Independent watchdog (IWDG) peripheral:           
//    9   *           - Prescaler and Counter configuration
//   10   *           - IWDG activation
//   11   *
//   12   *  @verbatim  
//   13   *  
//   14   *          ===================================================================
//   15   *                                     IWDG features
//   16   *          ===================================================================
//   17   *    
//   18   *          The IWDG can be started by either software or hardware (configurable
//   19   *          through option byte).
//   20   *            
//   21   *          The IWDG is clocked by its own dedicated low-speed clock (LSI) and
//   22   *          thus stays active even if the main clock fails.
//   23   *          Once the IWDG is started, the LSI is forced ON and cannot be disabled
//   24   *          (LSI cannot be disabled too), and the counter starts counting down from 
//   25   *          the reset value of 0xFF. When it reaches the end of count value (0x00)
//   26   *          a system reset is generated.
//   27   *          The IWDG counter should be reloaded at regular intervals to prevent
//   28   *          an MCU reset.
//   29   *                           
//   30   *          The IWDG is implemented in the VDD voltage domain that is still functional
//   31   *          in Halt and Active Halt mode depending on the configuration of the IWDG_HALT
//   32   *          option byte. (IWDG reset can wake-up from Halt).          
//   33   *            
//   34   *          IWDGF flag in RST_SR register can be used to inform when a IWDG
//   35   *          reset occurs.
//   36   *            
//   37   *          Min-max timeout value @38KHz (LSI): 0.10 ms / ~1.724s
//   38   *          The IWDG timeout may vary due to LSI frequency dispersion. STM8L15x
//   39   *          devices provide the capability to measure the LSI frequency (LSI clock
//   40   *          connected internally to TIM2 CH1 input capture). The measured value
//   41   *          can be used to have an IWDG timeout with an acceptable accuracy. 
//   42   *          For more information, please refer to the STM8L15x Reference manual
//   43   *          
//   44   *                            
//   45   *          ===================================================================
//   46   *                                 How to use this driver
//   47   *          ===================================================================
//   48   *          1. Enable write access to IWDG_PR and IWDG_RLR registers using
//   49   *             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
//   50   *               
//   51   *          2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
//   52   *            
//   53   *          3. Configure the IWDG counter value using IWDG_SetReload() function.
//   54   *             This value will be loaded in the IWDG counter each time the counter
//   55   *             is reloaded, then the IWDG will start counting down from this value.
//   56   *            
//   57   *          4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
//   58   *             in software mode (no need to enable the LSI, it will be enabled
//   59   *             by hardware)
//   60   *             
//   61   *          5. Then the application program must reload the IWDG counter at regular
//   62   *             intervals during normal operation to prevent an MCU reset, using
//   63   *             IWDG_ReloadCounter() function.      
//   64   *          
//   65   *  @endverbatim
//   66   *    
//   67   ******************************************************************************
//   68   *
//   69   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
//   70   * You may not use this file except in compliance with the License.
//   71   * You may obtain a copy of the License at:
//   72   *
//   73   *        http://www.st.com/software_license_agreement_liberty_v2
//   74   *
//   75   * Unless required by applicable law or agreed to in writing, software 
//   76   * distributed under the License is distributed on an "AS IS" BASIS, 
//   77   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//   78   * See the License for the specific language governing permissions and
//   79   * limitations under the License.
//   80   *
//   81   ******************************************************************************
//   82   */
//   83 
//   84 /* Includes ------------------------------------------------------------------*/
//   85 #include "stm8l15x_iwdg.h"
//   86 
//   87 /** @addtogroup STM8L15x_StdPeriph_Driver
//   88   * @{
//   89   */
//   90   
//   91 /** @defgroup IWDG 
//   92   * @brief IWDG driver modules
//   93   * @{
//   94   */ 
//   95 /* Private typedef -----------------------------------------------------------*/
//   96 /* Private define ------------------------------------------------------------*/
//   97 /* Private macro -------------------------------------------------------------*/
//   98 /* Private function prototypes -----------------------------------------------*/
//   99 /* Private functions ---------------------------------------------------------*/
//  100 
//  101 /** @defgroup IWDG_Private_Functions
//  102   * @{
//  103   */
//  104 
//  105 /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
//  106  *  @brief   Prescaler and Counter configuration functions
//  107  *
//  108 @verbatim   
//  109  ===============================================================================
//  110                   Prescaler and Counter configuration functions
//  111  ===============================================================================  
//  112 
//  113 @endverbatim
//  114   * @{
//  115   */
//  116   
//  117 /**
//  118   * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
//  119   * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
//  120   *          This parameter can be one of the following values:
//  121   *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
//  122   *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
//  123   * @retval None
//  124   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  125 void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
//  126 {
//  127   /* Check the parameters */
//  128   assert_param(IS_IWDG_WRITE_ACCESS_MODE(IWDG_WriteAccess));
//  129   IWDG->KR = IWDG_WriteAccess; /* Write Access */
IWDG_WriteAccessCmd:
        LD        L:0x50e0, A
//  130 }
        RET
//  131 
//  132 /**
//  133   * @brief  Sets IWDG Prescaler value.
//  134   * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
//  135   *          This parameter can be one of the following values:
//  136   *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
//  137   *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
//  138   *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
//  139   *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
//  140   *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
//  141   *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
//  142   *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
//  143   * @retval None
//  144   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  145 void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
//  146 {
//  147   /* Check the parameters */
//  148   assert_param(IS_IWDG_PRESCALER_VALUE(IWDG_Prescaler));
//  149   IWDG->PR = IWDG_Prescaler;
IWDG_SetPrescaler:
        LD        L:0x50e1, A
//  150 }
        RET
//  151 
//  152 /**
//  153   * @brief  Sets IWDG Reload value.
//  154   * @note   Write access should be enabled
//  155   * @param  IWDG_Reload : Reload register value.
//  156   *         This parameter must be a number between 0 and 0xFF.
//  157   * @retval None
//  158   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  159 void IWDG_SetReload(uint8_t IWDG_Reload)
//  160 {
//  161   IWDG->RLR = IWDG_Reload;
IWDG_SetReload:
        LD        L:0x50e2, A
//  162 }
        RET
//  163 
//  164 /**
//  165   * @brief  Reloads IWDG counter with value defined in the reload register
//  166   *         (write access to IWDG_PR and IWDG_RLR registers disabled).
//  167   * @param  None
//  168   * @retval None
//  169   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  170 void IWDG_ReloadCounter(void)
//  171 {
//  172   IWDG->KR = IWDG_KEY_REFRESH;
IWDG_ReloadCounter:
        MOV       L:0x50e0, #0xaa
//  173 }
        RET
//  174 
//  175 /**
//  176   * @}
//  177   */
//  178 
//  179 /** @defgroup IWDG_Group2 IWDG activation function
//  180  *  @brief   IWDG activation function 
//  181  *
//  182 @verbatim   
//  183  ===============================================================================
//  184                           IWDG activation function
//  185  ===============================================================================  
//  186 
//  187 @endverbatim
//  188   * @{
//  189   */
//  190 
//  191 /**
//  192   * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
//  193   * @param  None
//  194   * @retval None
//  195   */

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  196 void IWDG_Enable(void)
//  197 {
//  198   IWDG->KR = IWDG_KEY_ENABLE;
IWDG_Enable:
        MOV       L:0x50e0, #0xcc
//  199 }
        RET

        SECTION VREGS:DATA:REORDER:NOROOT(0)

        END
//  200 
//  201 /**
//  202   * @}
//  203   */
//  204 
//  205 /**
//  206   * @}
//  207   */
//  208   
//  209 /**
//  210   * @}
//  211   */
//  212 
//  213 /**
//  214   * @}
//  215   */
//  216 
//  217 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
// 
// 22 bytes in section .near_func.text
// 
// 22 bytes of CODE memory
//
//Errors: none
//Warnings: none
