///////////////////////////////////////////////////////////////////////////////
//
// IAR C/C++ Compiler V2.10.4.157 for STM8                10/Aug/2020  13:50:17
// Copyright 2010-2015 IAR Systems AB.
//
//    Source file  =  F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\bsp_time.c
//    Command line =  
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\bsp_time.c -e -Ol --no_cse
//        --no_unroll --no_inline --no_code_motion --no_tbaa --no_cross_call
//        --debug --code_model small --data_model medium -o
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\Obj\ --dlib_config
//        E:\IAR\stm8\LIB\dlstm8smf.h -lB
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\inc\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\FWLIB\src\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\USER\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\radio\ -I
//        F:\2-Lora\Code\stm8l151K6T6-WLAN\SX1278\ --vregs 16
//    List file    =  F:\2-Lora\Code\stm8l151K6T6-WLAN\Debug\List\bsp_time.s
//
///////////////////////////////////////////////////////////////////////////////

        EXTERN ?b0
        EXTERN ?dec32_l0_l0
        EXTERN ?epilogue_l2_l3
        EXTERN ?fcasts16f32_x_l0
        EXTERN ?fdiv32_l0_dc32_l1
        EXTERN ?fdiv32_l0_l0_dc32
        EXTERN ?fdiv32_l0_l0_l1
        EXTERN ?load32_0x_l0
        EXTERN ?load32_l0_0x
        EXTERN ?mov_l0_l1
        EXTERN ?mov_l1_l0
        EXTERN ?mov_l1_l2
        EXTERN ?mov_l1_l3
        EXTERN ?mov_l2_l0
        EXTERN ?mov_l3_l0
        EXTERN ?push_l2
        EXTERN ?push_l3
        EXTERN ?w0
        EXTERN ?w1
        EXTERN ?w2
        EXTERN ?w3
        EXTERN CLK_GetFlagStatus
        EXTERN CLK_GetSYSCLKSource
        EXTERN CLK_LSICmd
        EXTERN CLK_PeripheralClockConfig
        EXTERN CLK_RTCClockConfig
        EXTERN CLK_SYSCLKDivConfig
        EXTERN CLK_SYSCLKSourceConfig
        EXTERN CLK_SYSCLKSourceSwitchCmd
        EXTERN RTC_ITConfig
        EXTERN RTC_SetWakeUpCounter
        EXTERN RTC_WakeUpClockConfig
        EXTERN RTC_WakeUpCmd
        EXTERN pow

        PUBLIC DelayMs
        PUBLIC RtcConfig
        PUBLIC SoftDelayMs
        PUBLIC bsp_DelayMS
        PUBLIC bsp_clk_init
        PUBLIC bsp_delay_ms
        PUBLIC bsp_delay_s
        PUBLIC bsp_time2_init
        PUBLIC bsp_time4_init
        PUBLIC time_count2
        PUBLIC time_count4

// F:\2-Lora\Code\stm8l151K6T6-WLAN\BSP\bsp_time.c
//    1 #include "bsp_time.h"

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//    2 u32 time_count4 = 0;
time_count4:
        DS8 4

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//    3 u16 time_count2 = 0;
time_count2:
        DS8 2

        SECTION `.near.bss`:DATA:REORDER:NOROOT(0)
//    4 u16 DelayMs = 0;
DelayMs:
        DS8 2
//    5 /*************系统时钟***********************/

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//    6 void bsp_clk_init(void)
//    7 {
//    8 //#if(1)
//    9 //      #if AUTO_SWITCH
//   10 //          CLK->SWCR |= 0x02;
//   11 //          CLK->SWR = 0x04;
//   12 //          asm("NOP");
//   13 //          CLK->CKDIVR = 0x00;
//   14 //      #else
//   15 //          CLK->SWR = 0x04;
//   16 //          while((CLK->ECKCR & 0x02)==0);
//   17 //          CLK->SWCR |= 0x02;
//   18 //          while(!(CLK->SCSR & 0x04));
//   19 //          asm("NOP");
//   20 //          CLK->CKDIVR = SYSDIV;
//   21 //      #endif
//   22 //#else
//   23 //      CLK_SYSCLKSourceSwitchCmd(ENABLE);
//   24 //      CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSE);
//   25 //      while(CLK_GetSYSCLKSource()!=CLK_SYSCLKSource_HSE);
//   26 //      asm("NOP");
//   27 //      CLK->CKDIVR = 0x00;
//   28 //#endif
//   29 //CLK->CSSR |= 0x01;
//   30 //asm("NOP");
//   31 
//   32   CLK_SYSCLKSourceSwitchCmd(ENABLE);
bsp_clk_init:
        LD        A, #0x1
        CALL      L:CLK_SYSCLKSourceSwitchCmd
//   33     CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSI);
        LD        A, #0x1
        CALL      L:CLK_SYSCLKSourceConfig
//   34     /* 系统时钟分频*/
//   35     CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1);//之前是CLK_SYSCLKDiv_1
        CLR       A
        CALL      L:CLK_SYSCLKDivConfig
//   36     while (CLK_GetSYSCLKSource() != CLK_SYSCLKSource_HSI)
??bsp_clk_init_0:
        CALL      L:CLK_GetSYSCLKSource
        CP        A, #0x1
        JRNE      L:??bsp_clk_init_0
//   37         {}
//   38 }
        RET
//   39 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   40 void bsp_time4_init(void)
//   41 {
bsp_time4_init:
        CALL      L:?push_l2
        CALL      L:?push_l3
//   42       CLK_PeripheralClockConfig(CLK_Peripheral_TIM4,ENABLE);//CLK->PCKENR1 = 0x04;//使能定时器时钟
        MOV       S:?b0, #0x1
        LD        A, #0x2
        CALL      L:CLK_PeripheralClockConfig
//   43       TIM4->PSCR = TIMER4_DIV;//预分频
        MOV       L:0x52e8, #0x7
//   44       TIM4->CR1 = 0x85;//工作模式
        MOV       L:0x52e0, #0x85
//   45       TIM4->IER = 0x01;//定时器中断使能
        MOV       L:0x52e4, #0x1
//   46       TIM4->ARR = TIMER4_ARR;//自动重载的值
        CLRW      X
        LDW       S:?w3, X
        LDW       S:?w2, X
        CLRW      X
        LDW       S:?w1, X
        LDW       X, #0x4000
        LDW       S:?w0, X
        CALL      L:pow
        CALL      L:?mov_l2_l0
        CLRW      X
        LDW       S:?w3, X
        LDW       X, #0x40e0
        LDW       S:?w2, X
        CLRW      X
        LDW       S:?w1, X
        LDW       X, #0x4000
        LDW       S:?w0, X
        CALL      L:pow
        CALL      L:?mov_l3_l0
        CALL      L:?mov_l1_l2
        CALL      L:?fdiv32_l0_dc32_l1
        DATA
        DC32      0x4b742400
        CODE
        CALL      L:?mov_l1_l3
        CALL      L:?fdiv32_l0_l0_l1
        CALL      L:?fdiv32_l0_l0_dc32
        DATA
        DC32      0x447a0000
        CODE
        CALL      L:?fcasts16f32_x_l0
        LD        A, XL
        LD        L:0x52e9, A
//   47 }
        JP        L:?epilogue_l2_l3
//   48 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   49 void bsp_time2_init(void)
//   50 {
//   51       CLK->PCKENR1 = 0x05;//使能定时器时钟
bsp_time2_init:
        MOV       L:0x50c3, #0x5
//   52       TIM2->PSCR = 0x0E;//预分频
        MOV       L:0x525e, #0xe
//   53       TIM2->CR1 = 0x85;//工作模式
        MOV       L:0x5250, #0x85
//   54       TIM2->IER = 0x01;//定时器中断使能
        MOV       L:0x5255, #0x1
//   55       TIM2->CNTRH = 0x00;//自动重载的值
        MOV       L:0x525c, #0x0
//   56       TIM2->CNTRL = 0x00;
        MOV       L:0x525d, #0x0
//   57       TIM2->ARRH = 0x03;
        MOV       L:0x525f, #0x3
//   58       TIM2->ARRL = 0xE8;
        MOV       L:0x5260, #0xe8
//   59 
//   60 }
        RET
//   61 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   62 void RtcConfig(void)
//   63 {
//   64 
//   65     CLK_LSICmd(ENABLE);
RtcConfig:
        LD        A, #0x1
        CALL      L:CLK_LSICmd
//   66     while (CLK_GetFlagStatus(CLK_FLAG_LSIRDY) == RESET);
??RtcConfig_0:
        LD        A, #0x13
        CALL      L:CLK_GetFlagStatus
        CP        A, #0x0
        JREQ      L:??RtcConfig_0
//   67     CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE);
        MOV       S:?b0, #0x1
        LD        A, #0x12
        CALL      L:CLK_PeripheralClockConfig
//   68     CLK_RTCClockConfig(CLK_RTCCLKSource_LSI, CLK_RTCCLKDiv_1);//38Khz
        CLR       S:?b0
        LD        A, #0x4
        CALL      L:CLK_RTCClockConfig
//   69     RTC_WakeUpCmd(DISABLE);
        CLR       A
        CALL      L:RTC_WakeUpCmd
//   70     RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div16);//16分频=2.375Khz
        CLR       A
        CALL      L:RTC_WakeUpClockConfig
//   71     //RTC_SetWakeUpCounter(8);//1s
//   72     RTC_SetWakeUpCounter(2);
        LDW       X, #0x2
        CALL      L:RTC_SetWakeUpCounter
//   73     RTC_ITConfig(RTC_IT_WUT, ENABLE);
        LD        A, #0x1
        LDW       X, #0x40
        CALL      L:RTC_ITConfig
//   74     RTC_WakeUpCmd(ENABLE);
        LD        A, #0x1
        JP        L:RTC_WakeUpCmd
//   75 
//   76 }
//   77 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   78 void bsp_delay_ms(u16 ms)
//   79 {
//   80      time_count4 = ms;
bsp_delay_ms:
        LDW       S:?w1, X
        CLRW      X
        LDW       S:?w0, X
        LDW       X, #time_count4
        CALL      L:?load32_0x_l0
//   81      while(1)
//   82      {
//   83        if(time_count4==0)
??bsp_delay_ms_0:
        LDW       X, #time_count4
        CALL      L:?load32_l0_0x
        LDW       X, S:?w0
        CPW       X, #0x0
        JRNE      L:??bsp_delay_ms_1
        LDW       X, S:?w1
        CPW       X, #0x0
??bsp_delay_ms_1:
        JRNE      L:??bsp_delay_ms_0
//   84        {
//   85           break;
//   86        }
//   87      }
//   88 }
        RET
//   89 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//   90 void bsp_delay_s(u16 s)
//   91 {
//   92      time_count2 = s;
bsp_delay_s:
        LDW       L:time_count2, X
//   93      while(1)
//   94      {
//   95        if(time_count2==0)
??bsp_delay_s_0:
        LDW       X, L:time_count2
        TNZW      X
        JRNE      L:??bsp_delay_s_0
//   96        {
//   97           break;
//   98        }
//   99      }
//  100 }
        RET
//  101 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  102 void bsp_DelayMS(uint16_t ms)
//  103 {
//  104     DelayMs = ms;
bsp_DelayMS:
        LDW       L:DelayMs, X
//  105     while(DelayMs);
??bsp_DelayMS_0:
        LDW       X, L:DelayMs
        TNZW      X
        JRNE      L:??bsp_DelayMS_0
//  106 }
        RET
//  107 

        SECTION `.near_func.text`:CODE:REORDER:NOROOT(0)
        CODE
//  108 void SoftDelayMs(u32 ms)
//  109 {
//  110   int i=0,j=0;
SoftDelayMs:
        CLRW      Y
        CLRW      X
//  111   while(ms--)
??SoftDelayMs_0:
        CALL      L:?mov_l1_l0
        CALL      L:?mov_l0_l1
        CALL      L:?dec32_l0_l0
        LDW       X, S:?w2
        CPW       X, #0x0
        JRNE      L:??SoftDelayMs_1
        LDW       X, S:?w3
        CPW       X, #0x0
??SoftDelayMs_1:
        JREQ      L:??SoftDelayMs_2
//  112   {
//  113     for(i=0;i<16;i++)
        CLRW      Y
        JRA       L:??SoftDelayMs_3
//  114       for(j=0;j<1000;j++)
??SoftDelayMs_4:
        INCW      X
??SoftDelayMs_5:
        CPW       X, #0x3e8
        JRSLT     L:??SoftDelayMs_4
        INCW      Y
??SoftDelayMs_3:
        CPW       Y, #0x10
        JRSGE     L:??SoftDelayMs_0
        CLRW      X
        JRA       L:??SoftDelayMs_5
//  115       {
//  116         ;
//  117       }
//  118   }
//  119 }
??SoftDelayMs_2:
        RET

        SECTION VREGS:DATA:REORDER:NOROOT(0)

        END
// 
//   8 bytes in section .near.bss
// 313 bytes in section .near_func.text
// 
// 313 bytes of CODE memory
//   8 bytes of DATA memory
//
//Errors: none
//Warnings: none
